Closing the Gap Between ASIC & Custom

Closing the Gap Between ASIC & Custom

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This book carefully details design tools and techniques for high-performance ASIC design. Using these techniques, the performance of ASIC designs can be improved by two to three times. Important topics include: Improving performance through microarchitecture; Timing-driven floorplanning; Controlling and exploiting clock skew; High performance latch-based design in an ASIC methodology; Automatically identifying and synthesizing complex logic gates; Automated cell sizing to increase performance and reduce power; Controlling process variation.These techniques are illustrated by designs running two to three times the speed of typical ASICs in the same process generation.Chapter 7 examines an automated approach to changing flip-flop based gate netlists to use latches, in a standard cell ASIC flow ... [1] Benschneider, B.J., et al., aquot;A 300-MHz 64-b Quad-Issue CMOS RISC Microprocessor, aquot; IEEE Journal of Solid-State Circuits, vol. ... [2] Cadence, aquot;Theory of Operation: Transparent Latches, aquot; Pearl User Guide, 1998, pp. ... [4] Hauck, C., and Cheng, C. aquot;VLSI Implementation of a Portable 266MHz 32-Bit RISC Core, aquot; Microprocessor Report, November 200 1 .

Title:Closing the Gap Between ASIC & Custom
Author: David Chinnery, Kurt Keutzer
Publisher:Springer Science & Business Media - 2002-06-30

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